
Micron, Virginia
Lead Project Owner
May 2022 - Nov 2023
- Managed leadership projects (budgeted 50 million USD) across different sites globally to enhance manufacturing, yield, quality, and cost performance of products.
- Developed process improvement strategies by driving standardization programs, Network alignment Projects across different sites located globally (Malaysia, Taiwan, Singapore, Offshore Assembly) by collaborating with cross functional teams, OSATs and aligning to common plans

Micron, Singapore
Product owner/ Network Program Manager
June 2018 - May 2022
- Executed Continuous Improvement projects to reduce Cost of Non- Confirmation, Poor Execution (CONC, COPE).
- Led a cross-functional team to reduce defect ratio by using the DMAIC approach and improved yield to 99.8%, thereby clearing non-confirming lots with a tight deadline for shipments by collaborating with a wide range of personnel in relevant departments including manufacturing, planning, Technology development, Quality, and reliability, change management to develop and ship end products on a timely basis.
- Lead process improvement -lean six sigma projects to reduce waste and clearing WIP, thereby generating cash flow.
- Evaluating time-bound complex problems by aligning divergent stakeholder teams to a common plan and implementing corrective actions using SPC, FMEA, root cause analysis.

AMD, Singapore
Test Engineer
June 2017 - March 2018
- Led project based on Implementation of a successful model on improving yield by 2% by developing an Intelligent feedback system to benefit business gains by 1.03% through better characterization loop.
- Assisted Product engineers in bringing up the motherboards for System Level Test (SLT) and production mainly through different diagnostic bring ups including IC bring-up, testing and characterization.

NTU, Singapore – TUM, Germany
Master of Science – Integrated Circuit Design
Aug 2016 - March 2018
- Awarded "DAAD Scholarship for Outstanding Performance in academics in Master of Science"
- Awarded "TUM (Asia campus scholar- MSc Integrated Circuit Design)"
- GPA: 4.04/5.0, 1st Class of Honours, with Distinction

Bhilai Institute Technology, CSVTU University, India
Bachelor of Engineering, Electronics and Telecommunication Engineering
Aug 2012 - June 2016
- University Merit Rank Holder, Gold Medallist
- Published 6 research papers in international journals with Impact factors greater than 6
- GPA: 9.28/10, 1st Class of Honours, with Distinction
©2025 Rupal Jain